The present invention relates to a semiconductor device composed of a first semiconductor chip having a first LSI and a second semiconductor chip having a second LSI, which have been connected to each other by face down bonding, and to a method of manufacturing the semiconductor device.
In an effort to implement further miniaturized LSI semiconductor devices at lower cost, there has recently been proposed a semiconductor device composed of semiconductor chips having respective LSIs with different functions or formed by different processes, which have been bonded to each other by a face down method.
A description will now be given to the conventional LSI semiconductor device with reference to FIG. 8.
First internal electrodes 111 and bonding pads 112 are formed on a first semiconductor chip 110 having a first LSI, while second internal electrodes 121 are formed on a second semiconductor chip 120 having a second LSI. The first internal electrodes 111 of the first semiconductor chip 110 and the second internal electrodes 121 of the second semiconductor chip 120 are electrically connected to each other via bumps 122 made of solder. An insulating resin 130 is filled in the space between the first and second semiconductor chips 110 and 120, thereby integrating the first and second semiconductor chips 110 and 120.
The first semiconductor chip 110 is fixed to a die pad 131 of a lead frame by using a resin. The bonding pads 112 of the first semiconductor chip 110 are electrically connected to outer leads 132 of the lead frame by bonding wires 133. The first and second semiconductor chips 110 and 120, the bonding wires 133, the die pad 131, and parts of the outer leads 132 are packaged by using a molding resin.
A method of manufacturing the foregoing semiconductor device will be described with reference to FIGS. 8 and 9.
First, as shown in FIGS. 8 and 9, the first internal electrodes 111 and the bonding pads 112 are formed on the first semiconductor chips 110 having the first LSIs, while the second internal electrodes 121 are formed on the second semiconductor chips 120 having the second LSIs, followed by the formation of the bumps 122 made of solder on the second internal electrodes 121. Dicing is then performed with respect to a wafer on which the second semiconductor chips 120 are formed so that the second semiconductor chips 120 are separated from each other. Thereafter, the individual second semiconductor chips 120 are positioned over the first semiconductor chips 110 formed on a wafer.
Next, as shown in FIG. 9, the bumps 122 on the second semiconductor chips 120 are bonded to the first internal electrodes 111 of the first semiconductor chips 110. Dicing is then performed with respect to the wafer on which the first semiconductor chips 110 are formed so that the first semiconductor chips 110 are separated from each other.
Next, as shown in FIG. 8, the insulating resin 130 is filled in the space between the first and second semiconductor chips 110 and 120. Subsequently, the first semiconductor chip 110 is fixed to the die pad 131 of the lead frame by using a resin, while the bonding pads 112 of the first semiconductor chip 110 are connected to the outer leads 132 by the bonding wires 133. Thereafter, the first and second semiconductor chips 110 and 120, the bonding wires 133, the die pad 131, and parts of the outer leads 132 are packaged by using the molding resin 135, resulting in the conventional semiconductor device.
In accordance with the foregoing method of manufacturing the conventional semiconductor device, however, pure water used during the dicing of the wafer on which the first semiconductor chips 110 are formed enters the space between the first semiconductor chips 110 and the second semiconductor chips 120, which necessitates the step of removing the pure water by means of an oven or the like. Moreover, a shearing stress along the plane may be produced under the pressure of the pure water supplied during the dicing of the wafer on which the first semiconductor chips are formed and placed on the connecting portion between the first semiconductor chip 110 and the second semiconductor chip 120. Furthermore, silicon dust may be produced in the step of dicing the wafer on which the first semiconductor chips 110 are formed and enter the space between the first and second semiconductor chips 110 and 120, resulting in a first problem of degraded reliability and lower yield of the semiconductor device.
In the semiconductor device composed of the first semiconductor chip 110 having the first LSI and the second semiconductor chip 120 having the second LSI, which have been connected to each other via the bumps 122, it is necessary to coincide the positions of the first internal electrodes 111 of the first semiconductor chip 110 with the positions of the second internal electrodes 121 of the second semiconductor chip 120. This elongates a wire connecting a functional block formed in the first LSI of the first semiconductor chip 110 to the first internal electrode 111 or a wire connecting a functional block formed in the second LSI of the second semiconductor chip 120 to the second internal electrode 121, resulting in a signal delay in the first or second LSI.
To reduce the length of the wire connecting the functional block formed in the first LSI of the first semiconductor chip 110 to the first internal electrode 111, there has been devised a method of offsetting the positions of the first internal electrodes 111 formed on the first semiconductor chip 110 from the center of the first semiconductor chip 110 by bringing the first internal electrodes 111 closer to the functional block formed in the first LSI.
However, when the positions of the first internal electrodes 111 are offset from the center of the first semiconductor chip 110, the distance between one side face of the second semiconductor chip 120 and the corresponding outer face of the molding resin 135 differs from the distance between another side face of the second semiconductor chip 120 and the corresponding outer face of the molding resin 135, because the center position of the first semiconductor chip 110 should coincide with the center position of the second semiconductor chip 120. Accordingly, the amount of the molding resin 135 present on the sides of the second semiconductor chip 120 differs from one portion to another, resulting in different curing compressive stresses placed on the side faces of the second semiconductor chip 120 when the molding resin 135 is cured. Specifically, the curing compressive stress is larger in a region in which the molding resin 135 exists in a larger amount (the region indicated by A in FIG. 10(b)) than in a region in which the molding resin 135 exists in a smaller amount (the region indicated by B in FIG. 10(b)). Although the temperature of the molding resin 135 increases in mounting the semiconductor device on a printed circuit board and the molding resin 135 is thermally expanded thereby, a thermal stress produced by the thermal expansion and placed on the second semiconductor chip 120 also differs from one side face to another. Specifically, the thermal stress is larger in the region A in which the molding resin 135 exists in a larger amount than in the region B in which the molding resin 135 exists in a smaller amount. Accordingly, the curing compressive stress and thermal stress placed on the side face a of the second semiconductor chip 120 corresponding to the region A in which the molding resin 135 exists in a larger amount are larger than those place on the side face b corresponding to the region B in which the molding resin 135 exists in a smaller amount. Consequently, a shearing stress along the plane resulting from different curing compressive stresses and different thermal stresses is placed on the connecting portion between the first and second semiconductor chips 110 and 120, presenting a second problem of degraded reliability and lower yield of the semiconductor device.